Extended WatchdogConfig (UE9 Only)

Controls a firmware based watchdog timer. Unattended systems requiring maximum up-time might use this capability to reset the UE9 or the entire system. When any of the options are enabled, an internal timer is enabled which resets on any incoming Control communication. If this timer reaches the defined TimeoutPeriod before being reset, the specified actions will occur. Note that while streaming, data is only going out of the Control processor, so some other Control command will have to be called periodically to reset the watchdog timer.

If the watchdog is accidentally configured to reset the processors with a very low timeout period (such as 1 second), it could be difficult to establish any communication with the device. In such a case, the reset-to-default jumper can be used to turn off the watchdog (sets bytes 7-10 to 0). Power up the UE9 with a short from FIO2<=>SCL, then remove the jumper and power cycle the device again. This also returns Comm (Section 5.2.1) and Control (Section 5.3.2) settings to factory defaults.

The watchdog settings (bytes 7-10) are stored in non-volatile flash memory, so every call to this function where settings are changed causes a flash erase/write. The Control flash has a rated endurance of at least 20000 writes, which is plenty for reasonable operation, but if this function is called in a high-speed loop the flash could be damaged.

New features in the extended version:

• Initial roll time: When the UE9 resets a longer timeout will be used. Once the watchdog has been reset the normal roll time will be used.

• Strict: Allow a specific key to be specified, so that only calling the WDT_Clear function with the matching key will reset the WatchDog.

WatchdogOptions: The watchdog is enabled when this byte is nonzero. Set the appropriate bit to reset either or both processors, update the state of 1 or 2 digital I/O, or update 1 or both DACs.

TimeoutPeriod: The watchdog timer is reset to zero on any incoming Control communication. Note that most functions consist of a write and read, but StreamData is outgoing only and does not reset the watchdog. If the watchdog timer is not reset before it counts up to TimeoutPeriod, the actions specified by WatchdogOptions will occur. The watchdog timer has a clock rate of about 1 Hz, so a TimeoutPeriod range of 1-65535 corresponds to about 1 to 65535 seconds.

Initial TimeoutPeriod: Timeout period that will be used until the first WatchDog clear.

DIOConfig#: Determines which digital I/O is affected by the watchdog, and the state it is set to. The digital I/O # is a value from 0-22 according to the following: 0-7 => FIO0-FIO7, 8-15 => EIO0-EIO7, 16-19 => CIO0-CIO3, 20-22 => MIO0-MIO2

DAC#: Specifies values for the DACs on watchdog timeout. The UE9 has 12-bit analog outputs, so pass an output value between 0 and 4095, plus set bit 7 of the high byte accordingly. If Bit7 is set on either DAC, then both are enabled. To disable the DACs (set to high-impedance), bit 7 must be 0 for both DACs.

Strict Key: Specifies a 1 byte key that must be passed to WatchDog Clear if strict is enabled.