13.2.3 PWM Out with Phase [T-Series Datasheet]

Overview

T4 Capable DIO: DIO6, DIO7 (aka FIO6, FIO7)

T7 Capable DIO: DIO0, DIO2, DIO3, DIO4, DIO5 (aka FIO0, FIO2, FIO3, FIO4, FIO5)

T8 Capable DIO: DIO2, DIO3, DIO4, DIO5, DIO6, DIO7, DIO8, DIO11, DIO12 (aka FIO2, FIO3, FIO4, FIO5, FIO6, FIO7, EIO0, EIO3, EIO4)

Requires Clock Source: Yes

Index: 1

Streamable: No

This PWM Out with Phase Extended Feature is similar to the PWM Out DIO-EF, but allows for phase control.

Operation

PWM Output with Phase control generates PWM waveforms with the pulse positioned at different points in the period. This is achieved by setting the DIO line high and low relative to the clock source's count.

Clock#Frequency = CoreFrequency / DIO_EF_CLOCK#_DIVISOR
PWMFrequency = Clock#Frequency / DIO_EF_CLOCK#_ROLL_VALUE DutyCycle% = 100 * (DIO#_EF_CONFIG_A - DIO#_EF_CONFIG_B) / DIO_EF_CLOCK#_ROLL_VALUE PhaseOffset = 360º * DIO#_EF_CONFIG_A / DIO_EF_CLOCK#_ROLL_VALUE

When the count matches CONFIG_B, the DIO line will be set high. When the count matches CONFIG_A, the line will be set low. Therefore CONFIG_B minus CONFIG_A controls the duty cycle.

See the DIO-EF Clock Source section for more information about your device core frequency and DIO_EF clock source settings.

DIO_EF_CLOCK#_ROLL_VALUE is a 32-bit value for CLOCK0 and a 16-bit value for CLOCK1 & CLOCK2. A value of 0 corresponds to the max roll value of 2³² for the 32-bit clock or 2¹⁶ for 16-bit clocks.

The clock roll value can take up to one PWM period to update and this does not block subsequent commands from being processed. It is possible to finish updating DIO_EF_CONFIG_A or DIO_CONFIG_B to a value greater than the non-updated clock roll value (which is invalid) but less than the updated clock roll value (which is valid) and throw the error 2565: EF_VALUE_GREATER_THAN_PERIOD.

Potential fixes:

disable and re-enable the clock line before updating the clock roll value and duty cycle value.
Delay for greater than one "non-updated" PWM period between updating the clock roll value and updating the duty cycle value

Configure

DIO#_EF_ENABLE: 0 = Disable, 1 = Enable
DIO#_EF_INDEX: 1
DIO#_EF_CLOCK_SOURCE (formerly DIO#_EF_OPTIONS): Specify which clock source to use. 0 for Clock0, 1 for Clock1, or 2 for Clock2.
DIO#_EF_CONFIG_A: When the clock source's count matches this value the line will transition from high to low.
DIO#_EF_CONFIG_B: When the clock source's count matches this value the line will transition from low to high.
DIO#_EF_CONFIG_C: Not used.
DIO#_EF_CONFIG_D: Not used.

Update

The duty cycle can be updated at any time. To update, write the new value to CONFIG_A then CONFIG_B. The value written to CONFIG_A is stored until CONFIG_B is written. After writing CONFIG_B, the new value will be loaded at the start of the next period. Updates are glitch-less unless switching from a very high to very low duty cycle or a very low to very high duty cycle.

DIO#_EF_CONFIG_A: Values written here will set the new falling position. The new value will not take effect until CONFIG_B is written.
DIO#_EF_CONFIG_B: Values written here will set the new rising position. When CONFIG_B is written, the new CONFIG_A is also loaded.

Read

No information is returned by PWM Out with Phase.

Reset

Reset has no affect on this feature.

Example

See the PWM Out documentation for an example.