13.0 Digital I/O [T-Series Datasheet]
Overview
Basics: Individual digital I/O lines can be set to digital input or digital output. DIO is a generic name used for all digital I/O.
Common Uses: For wiring information on open-collector signals, driven signals, controlling relays, and mechanical switches, see the Digital I/O (App Note).
Device Control Basics:
All T-series device features are controlled by reading and writing Modbus TCP registers via Modbus TCP (either directly or through our LJM library).
We have register descriptions throughout documentation detailing relevant register names, starting addresses, types, and access permissions (read/write).
Most DIO registers have a UINT16 type meaning each register requires 16-bits to represent the associated data. Each entry in the device address space holds 16-bits of data, so most DIO registers take up one address space such as 2004 (FIO4 register). See the Modbus Map for related information.
See Section 3.0 Communication for other detailed communication information.
DIO Extended Features: T-series DIO Extended Features expose more complicated features such as:
Timers, Counters, PWM, Quadrature Input, and more.
Digital Communication Protocols: T-series DIO lines can also be used to communicate with a large number of sensors that require the use of various digital communication protocols. The T-series devices implement the following protocols:
I2C - Also reference the I2C Lua Library and Lua I2C Sensor examples.
Subsections
DIO Summary By Device
T4
Digital I/O: Up to 16 DIO lines (DIO4-DIO19)
8 flexible I/O (DIO4-DIO11)
8 dedicated I/O (DIO12-DIO19)
Logic Level: 3.3V (Adjustable using a LJTick-LVDigitalIO).
T7
Digital I/O: Up to 23 DIO lines (DIO0-DIO22)
Logic Level: 3.3V (Adjustable using a LJTick-LVDigitalIO).
T8
Digital I/O: Up to 20 DIO lines (DIO0-DIO19)
Logic Level: 3.3V (Adjustable using a LJTick-LVDigitalIO).
Usage
There are two ways to access the simple functionality of the DIO:
Read or write individual DIO channels one-at-a-time. Individual DIO channels are automatically configured.
Read or write multiple DIO channels at once with the DIO Bitmask Registers, which are manually configured.
Individual DIO Channels
Each T-Series device exposes:
The following drop-down boxes have more device specific information such as pin/channel mappings.
The LabJack T4 has up to 16 built-in digital input/output lines. They can be written/read as registers named DIO4-DIO19.
DIO4-DIO11 are flexible I/O lines. (See 13.1 Flexible I/O.) These are lines that can be configured for analog input or digital input/output:
Figure 13.0-1 T4 Flexible I/O
DIO12-DIO19 are dedicated (digital-only) I/O lines:
Figure 13.0-2 T4 Dedicated Digital I/O
The registers DIO4-DIO19 can also be accessed using their alternate register names, FIO4-7, EIO0-7, and CIO0-3:
Table 13.0-1. T4 DIO Mapping
DIO Name | Alternate Name | AIN Name |
|---|---|---|
N/A | N/A | AIN0 |
N/A | N/A | AIN1 |
N/A | N/A | AIN2 |
N/A | N/A | AIN3 |
DIO4 | FIO4 | AIN4 |
DIO5 | FIO5 | AIN5 |
DIO6 | FIO6 | AIN6 |
DIO7 | FIO7 | AIN7 |
DIO8 | EIO0 | AIN8 |
DIO9 | EIO1 | AIN9 |
DIO10 | EIO2 | AIN10 |
DIO11 | EIO3 | AIN11 |
DIO12 | EIO4 | N/A |
DIO13 | EIO5 | N/A |
DIO14 | EIO6 | N/A |
DIO15 | EIO7 | N/A |
DIO16 | CIO0 | N/A |
DIO17 | CIO1 | N/A |
DIO18 | CIO2 | N/A |
DIO19 | CIO3 | N/A |
Figure 13.0-3 T7 Digital I/O
The LabJack T7 has 23 built-in digital input/output lines. They can be written/read as registers named DIO0-DIO22. They can also accessed using their alternate register names: FIO0-7, EIO0-7, CIO0-3, and MIO0-2:
Table 13.0-2. T7 DIO Mapping
DIO Name | Alternate Name |
|---|---|
DIO0 | FIO0 |
DIO1 | FIO1 |
DIO2 | FIO2 |
DIO3 | FIO3 |
DIO4 | FIO4 |
DIO5 | FIO5 |
DIO6 | FIO6 |
DIO7 | FIO7 |
DIO8 | EIO0 |
DIO9 | EIO1 |
DIO10 | EIO2 |
DIO11 | EIO3 |
DIO12 | EIO4 |
DIO13 | EIO5 |
DIO14 | EIO6 |
DIO15 | EIO7 |
DIO16 | CIO0 |
DIO17 | CIO1 |
DIO18 | CIO2 |
DIO19 | CIO3 |
DIO20 | MIO0 |
DIO21 | MIO1 |
DIO22 | MIO2 |
Figure 13.0-4 T8 Digital I/O
The LabJack T8 has 20 built-in digital input/output lines. They can be written/read as registers named DIO0-DIO19. They can also accessed using their alternate register names: FIO0-7, EIO0-7, and CIO0-3.
Table 13.0-3. T8 DIO Mapping
DIO Name | Alternate Name |
|---|---|
DIO0 | FIO0 |
DIO1 | FIO1 |
DIO2 | FIO2 |
DIO3 | FIO3 |
DIO4 | FIO4 |
DIO5 | FIO5 |
DIO6 | FIO6 |
DIO7 | FIO7 |
DIO8 | EIO0 |
DIO9 | EIO1 |
DIO10 | EIO2 |
DIO11 | EIO3 |
DIO12 | EIO4 |
DIO13 | EIO5 |
DIO14 | EIO6 |
DIO15 | EIO7 |
DIO16 | CIO0 |
DIO17 | CIO1 |
DIO18 | CIO2 |
DIO19 | CIO3 |
Examples
The individual DIO registers set both the state and direction; reads set the DIO to input and writes to output. To read a DIO without affecting its direction, see the DIO Bitmask section.
To set FIO4 to an output high (~3.3V) using LJM, write a 1 to address 2004 using a function such as eWriteAddress.
To set FIO6 to input and read the state using LJM, read address 2006 using a function such as eReadAddress.
Alternate Digital Channel Names
All DIO channels have alternate names. These names are typically printed on the device case and applicable accessories rather than the base DIO number.
Not all devices support every group of alternate channel names/registers. See the DIO Mapping tables in the previous section for more information.
Example:
Writing 0 to FIO4 (address 2004) is the same as writing 0 to DIO4 (address 2004).
DIO Bitmask Registers
The digital I/O bitmask registers allow for the direction (input or output) and state (high or low) of multiple digital I/O lines to be set during a single register write. Each bit in the value written to these registers corresponds to an individual I/O line on the device. The number of valid bits in the bitmask depends on which device is being used. To see which bits are valid for each device, see the above reference tables T4 DIO Mapping and T7 DIO Mapping.
The lower four bits of these DIO bitmask registers don't apply to the T4.
Writing DIO Bitmask Registers
DIO_INHIBIT, DIO_DIRECTION, and DIO_STATE should typically be written together. Each true bit in DIO_INHIBIT prevents a corresponding bit in DIO_DIRECTION and DIO_STATE from being modified. For more details about the DIO_INHIBIT register, see the examples section below, as well as the manual configuration section of the flexible I/O page.
The LJM multiple value functions provide an easy way to write DIO_INHIBIT, DIO_DIRECTION, and DIO_STATE in a single packet.
Write Example
To configure DIO4 and DIO5 as a digital outputs set to high, do the following:
Build a bitmask based on the DIO channel numbers being controlled. For this example we are controlling DIO channels 4 and 5. All of the following values are equivalent:
(1<<4) | (1<<5) , (2^4 + 2^5) , and 16 + 32 are all equal to 0b00110000, 0x30, and 48.Subtract the bitmask value 0x30 from a value with 23 bits of "1"s (0x7FFFFF)to calculate the value that needs to be written to the DIO_INHIBIT register:
0x7FFFFF - (1<<4)|(1<<5) which equals 0b11111111111111111001111, 0x7FFFCF, or 8388559Write the bitmask value 0x7FFFCF to the DIO_INHIBIT register to inhibit all DIO channels except 4 and 5.
Write the bitmask value 0x30 to the DIO_DIRECTION register to set the I/O lines as output.
Write the bitmask value 0x30 to the DIO_STATE register to have the two I/O lines output 3.3V.
Reading DIO Bitmask Registers
The typical workflow for reading the DIO Bitmask Registers is to only read DIO_STATE. This is because DIO_INHIBIT and DIO_DIRECTION are typically known.
DIO vs. FIO/EIO/CIO/MIO
DIO is a generic name used for all digital I/O. The DIO are subdivided into different groups called FIO, EIO, CIO, and MIO.
Sometimes these are referred to as different "ports". For example, FIO is an 8-bit port of digital I/O and EIO is a different 8-bit port of digital I/O. The different names (FIO vs. EIO vs. CIO vs. MIO) have little meaning, and generally you can call these all DIO0-DIO22 and consider them all the same. There are a couple details unique to different ports:
The source impedance of an FIO line is about 550 ohms, whereas the source impedance of EIO/CIO/MIO lines is about 180 ohms. Source impedance might be important when sourcing or sinking substantial currents, such as when controlling relays.
The MIO lines are automatically controlled when using analog input channel numbers from 16 to 127. This is for controlling external multiplexers or the Mux80 expansion board.
FIO/EIO/CIO/MIO Bitmask Registers
The following FIO/EIO/CIO/MIO bitmask registers are similar to the above DIO bitmask registers. However, instead of having a dedicated register designated for the inhibit bits, the inhibit bits are the upper 8-bits of each register.
Lower order bits of the FIO_STATE and FIO_DIRECTION have no affect on the T4.The MIO_STATE and MIO_DIRECTION registers have no affect on the T4 or T8.
Example:
To read the digital state of all FIO lines in a bitmask, read FIO_STATE. If the result is 0b11111011, FIO2 is logic low and all other FIO lines are logic high.
Example:
To set FIO1-7 to output, write a value of 0x01FF to FIO_DIRECTION. FIO0 is the least significant bit, so to prevent modification the corresponding inhibit bit is set with 0x01 in the most significant byte. The least significant byte is 0xFF, which is all 8 bits of FIO set to output.
Combination FIO/EIO/CIO/MIO State Registers
These registers are a combination of the FIO/EIO/CIO/MIO State registers.
Other Considerations
Specifications
See Appendix A-2 for specs including:
Low Level Input Voltage
High Level Input Voltage
Hysteresis Voltage
Maximum Input Voltage
Output Low Voltage
Output High Voltage
Short Circuit Current
Output Impedance
Streaming DIO
For details about which DIO registers can be streamed look at section 3.2 Stream Mode. In short, only the FIO/EIO/CIO/MIO State registers can be streamed because stream data is transferred as 16-bit values.
Electrical Overview
All digital I/O on T-series devices are tri-state and thus have 3 possible states: input, output-high, or output-low. Each bit of I/O can be configured individually:
When configured as an input, a bit has a ~100 kΩ pull-up resistor to 3.3 volts (all digital I/O are at least 5 volt tolerant).
When configured as output-high, a bit is connected to the internal 3.3 volt supply (through a series resistor).
When configured as output-low, a bit is connected to GND (through a series resistor).
T8 Only: In addition to the above settings, the T8 can disable the pull-ups and enable pulldowns:
By default all DIOs on the T8 have a pull-up enabled. Those pull-ups can be disabled using DIO_PULLUP_DISABLE.
By default all DIOs on the T8 have a pull-downs disabled. The pull-downs can be enabled using DIO_PULLDOWN_ENABLE.
If a DIO terminal is at about 3.3 volts, and you are not sure if it is set to input or output-high, a couple ways to tell are:
Look for a slight change on a terminal with nothing connected except a DMM. For example, a DMM measurement of an input might show 3.30V whereas that same terminal as output-high reads 3.31V.
Add a load resistor. If you add a 100k from FIO7 to GND, the terminal should measure about 1.6V for input and 3.3V for output-high.
See Appendix A-2 for more details.
By default, the DIO lines are digital I/O, but they can also be configured as PWM Output, Quadrature Input, Counters, etc. (See 13.2 DIO Extended Feature.)
Power-up Defaults
The default condition of the digital I/O can be configured using Kipling or programmatically. From the factory, all digital I/O are configured as inputs by default. Note that even if the default for a line is changed to output-high or output-low, there could be a small time (milliseconds) during boot-up where all digital I/O are in the factory default condition, or in the case of EIO0 a unique condition. See more details in the IO Config section.
If this brief time in the input state is a problem, consider adding a pull-down resistor. For example, a 10k resistor will form a voltage divider with the internal 100k to 3.3V and result in about 0.3V on the DIO terminal when in the input state. In the output-states, this 10k will be additional load on the output-high or output-low, but often is negligible.
Protection
All the digital I/O include an internal series resistor that provides overvoltage/short-circuit protection. These series resistors also limit the ability of these lines to sink or source current. Refer to Appendix A-2.
The fact that the digital I/O are specified as 5-volt tolerant means that 5 volts can be connected to a digital input without problems (see the actual limits in the specifications in Appendix A).
Increase logic level to 5V
On-board DACs: The DAC0 and DAC1 channels can be set to 5 volts, providing 2 output lines with such capability.
LabJack LJTick-DigitalOut5V: We sell the LJTick-DigitalOut5V that converts our 3.3V outputs to 5V outputs.
Logic Buffer IC: The surefire way to get 5 volts from a digital output is to add a simple logic buffer IC that is powered by 5 volts and recognizes 3.3 volts as a high input. Consider the CD74ACT541E from TI (or the inverting CD74ACT540E). All that is needed is a few wires to bring VS, GND, and the signal from the LabJack to the chip. This chip can level shift up to eight 0/3.3 volt signals to 0/5 volt signals and provides high output drive current (+/-24 mA).
Open-collector: In some cases, an open-collector style output can be used to get a 5V signal. To get a low set the line to output-low, and to get a high set the line to input. When the line is set to input, the voltage on the line is determined by a pull-up resistor. T-series devices have an internal ~100k resistor to 3.3V, but an external resistor can be added to a different voltage. Whether this will work depends on how much current the load is going to draw and what the required logic thresholds are. Say for example a 10k resistor is added from EIO0 to VS. EIO0 has an internal 100k pull-up to 3.3 volts and a series output resistance of about 180 ohms. Assume the load draws just a few microamps or less and thus is negligible. When EIO0 is set to input, there will be 100k to 3.3 volts in parallel with 10k to 5 volts, and thus the line will sit at about 4.85 volts. When the line is set to output-low, there will be 180 ohms in series with the 10k, so the line will be pulled down to about 0.1 volts.
Waveform Generation
DIO registers described on this page may be used for software-timed square/rectangular waveform output.
For other options, see the Waveform Generation App Note.
Reading the State of an Output
Reading an output will exhibit the following behaviors:
Reading from the DIO registers (address 2000-2022) will set the IO to input. Use DIO_STATE to read the state without affecting direction.
When reading the state of an output, the actual voltage, as measured behind the protection resistors (see the “Protection” section above), will be used to determine whether the line is logic high or low.
The voltage is read behind the protection resistors. This creates a voltage divider with the output circuitry. That divider causes the following behaviors:
An output-high will read HIGH even when the screw terminal is shorted to GND. Connecting a negative voltage may cause an output-high to read LOW.
A CIO or EIO line set to output-low will read HIGH when shorted to VS.
A FIO line set to output-low will read LOW when shorted to VS.
At this time is it not possible to read the latches that control whether the IO is attempting to drive high or low.
Do DIO Change State Automatically?
As described in Electrical Overview above, digital I/O on T-series devices are tri-state and thus have 3 possible states: input, output-high, or output-low. The DIO stay in their current state until told to go to some different state. There are various ways they could be told to go to a different state:
Some software sends a command telling a DIO to go to a different state.
Your Lua script running on the device tells a DIO to go to a different state.
The watchdog tells DIO to go to a different state.
The T7 reboots causing the DIO to go to the saved power-up condition.