2.9.1.11 - Period Measurement (16-Bit, Modes 12 & 13) [U3 Datasheet]

Similar to the 32-bit edge-to-edge timing modes described earlier (modes 2 & 3), except that hardware capture registers are used to record the edge times.  This limits the times to 16-bit values, but is accurate to the resolution of the clock, and not subject to any errors due to firmware processing delays.

To select a clock frequency, consider the longest expected period, and set the clock frequency such that the 16-bit registers will not overflow.  In other words, to measure a given signal frequency, you need to set your clock frequency low enough such that the overall period of the signal is less than 65535 * 1/TimerClockFrequency.  That equates to:

fclock  ≤  65535 * fsignal

Edge Rate Limits

This edge-detecting timer mode requires processing resources as an interrupt is required to handle each edge.  See more about edge rate limits in Section 2.9.2.