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Skip table of contents - Period Measurement (32-Bit, Modes 2 & 3) [U3 Datasheet]

Mode 2:  On every rising edge seen by the external pin, this mode records the number of clock cycles (clock frequency determined by TimerClockBase/TimerClockDivisor) between this rising edge and the previous rising edge.  The value is updated on every rising edge, so a read returns the time between the most recent pair of rising edges.

Mode 3 is the same except that falling edges are used instead of rising edges.

In this 32-bit mode, the processor must jump to an interrupt service routine to record the time, so small errors can occur if another interrupt is already in progress.  The possible error sources are:

  • Other edge interrupt timer modes (2/3/4/5/8/9/12/13).  If an interrupt is already being handled due to an edge on the other timer, delays of a few  microseconds are possible.
  • If a stream is in progress, every sample is acquired in a high-priority interrupt.  These interrupts could cause delays on the order of 10 microseconds.
  • The always active U3 system timer causes an interrupt 61 times per second.  If this interrupt happens to be in progress when the edge occurs, a delay of about 1 microsecond is possible.  If the software watchdog is enabled, the system timer interrupt takes longer to execute and a delay of a few microseconds is possible.

Note that the minimum measurable period is limited by the edge rate limit discussed in Section 2.9.2.

See Section 3.2.1 for a special condition if stream mode is used to acquire timer data in this mode.

Writing a value of zero to the timer performs a reset.  After reset, a read of the timer value will return zero until a new edge is detected.  If a timer is reset and read in the same function call, the read returns the value just before the reset.

Higher clock frequency gives better time resolution.  The downside to higher clock frequency is the max measurable period is shorter.  The default clock frequency is the max available frequency of 48 MHz.  If we divide 2^32 (this timer holds a 32-bit value) by 48M we get 89.5, so this default clock configuration can count a period as long as 89.5 seconds.  Thus the default 48 MHz clock is almost always the best choice.

Edge Rate Limits

This edge-detecting timer mode requires processing resources as an interrupt is required to handle each edge.  See more about edge rate limits in Section 2.9.2.

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