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Skip table of contents - Firmware Counter Input With Debounce (Mode 6) [U3 Datasheet]

Intended for frequencies less than 10 Hz, this mode adds a debounce feature to the firmware counter, which is particularly useful for signals from mechanical switches.  On every applicable edge seen by the external pin, this mode increments a 32-bit register.  Unlike the pure hardware counters, these timer counters require that the firmware jump to an interrupt service routine on each edge.

The debounce period is set by writing the timer value.  The low byte of the timer value is a number from 0-255 that specifies a debounce period in 16 ms increments (plus an extra 0-16 ms of variability):

Debounce Period = (0-16 ms) + (TimerValue * 16 ms)

In the high byte (bits 8-16) of the timer value, bit 0 determines whether negative edges (bit 0 clear) or positive edges (bit 0 set) are counted.

Assume this mode is enabled with a value of 1, meaning that the debounce period is 16-32 ms and negative edges will be counted.  When the input detects a negative edge, it increments the count by 1, and then waits 16-32 ms before re-arming the edge detector.  Any negative edges within the debounce period are ignored.  This is good behavior for a normally-high signal where the switch closure causes a brief low signal (see Section  The debounce period can be set long enough so that bouncing on both the switch closure and switch open is ignored.

Writing a value of zero to the timer performs a reset.  After reset, a read of the timer value will return zero until a new edge is detected.  If a timer is reset and read in the same function call, the read returns the value just before the reset.

Edge Rate Limits

This edge-detecting timer mode requires processing resources as an interrupt is required to handle each edge.  See more about edge rate limits in Section 2.9.2.

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