A-4 Analog Output [T-Series Datasheet]
Specifications for analog output channels (DAC0 and DAC1) are shown below.
T4
Table A4-1. T4 DAC Information. All specifications are at 25 °C and Vsupply = 5.0 V unless otherwise noted.
| Conditions | Min | Typical | Max | Units | |
|---|---|---|---|---|---|
| Nominal Output Range [1] | No Load | 0.01 | - | 4.98 | Volts |
| @ ±2.5 mA | 0.30 | - | 4.69 | Volts | |
| Resolution | - | - | 10 | - | Bits |
| Absolute Accuracy | 5% to 95%, No Load | - | ±0.15 | - | % FS |
| - | - | ±7.5 | - | mV | |
| Integral Linearity Error | - | - | - | ±1 | counts |
| Differential Linearity Error | - | - | ±0.1 | ±0.5 | counts |
| Noise [2] | - | - | ±1 | - | counts |
| Source Impedance [3] | - | - | 110 | ±10 | Ω |
| Current Limit [4] | Max to GND | - | 32 | - | mA |
| Time Constant | - | - | 1 | - | μs |
[1] Maximum and minimum analog output voltage is limited by the supply voltages (VS and GND). The specifications assume VS is 5.0 volts. Also, the ability of the DAC output buffer to driver voltages close to the power rails, decreases with increasing output current.
[2] Specified with no load and set to 0 V. Noise will increase with load and voltage, to a maximum of 3 counts @ 4V with a 100 Ω load. The DAC's ability to reject noise decreases as the output voltage nears the Vs supply.
[3] The source impedance is a combination of fixed resistance and the impedance from the output buffer. The impedance from the buffer will vary depending on the operating conditions. When set to 4 V with a 100 Ω load, Rs is ~ 112 Ω. When set to 4 V with a 10 kΩ load, Rs is ~110 Ω.
[4] The output buffer will limit current to about 30 mA and can maintain this value continuously without damage. Take, for example, a 1.5 ohm resistor from DAC0 to GND, with the internal source impedance of 110 ohms, and DAC0 set to 4.5V. A simple calculation would predict a current of 4.5/(110+1.5) = 40 mA, but the output buffer will limit the current to 32 mA.
T7
Table A4-2. T7 DAC Information. All specifications are at 25 °C and Vsupply = 5.0 V unless otherwise noted.
| Conditions | Min | Typical | Max | Units | |
|---|---|---|---|---|---|
| Nominal Output Range [5] | No Load | 0.01 | - | 4.99 | Volts |
| @ ±2.5 mA | 0.25 | - | 4.75 | Volts | |
| Resolution | - | - | 12 | - | Bits |
| Absolute Accuracy | 5% to 95% FS | - | ±0.06 | 0 | % FS |
| Integral Linearity Error | - | - | ±1.5 | ±2 | counts |
| Differential Linearity Error | - | - | ±0.25 | ±0.5 | counts |
| Noise [6] | - | - | ±100 | - | μV |
| Source Impedance [7] | - | - | 50 | - | Ω |
| Current Limit [8] | Max to GND | - | 20 | - | mA |
| Time Constant | - | - | 4 | - | μs |
[5] Maximum and minimum analog output voltage is limited by the supply voltages (VS and GND). The specifications assume VS is 5.0 volts. Also, the ability of the DAC output buffer to driver voltages close to the power rails, decreases with increasing output current.
[6] With load, the noise increases if operating too close to VS. With a 1000 ohm load, noise increases noticeably at 4.4V and higher. With a 330 ohm load, noise increases noticeably at 3.7V and higher. With a 100 ohm load, noise increases noticeably at 2.7V and higher.
[7] For currents up to about 8mA, this source impedance dominates the error due to loading. For example, if you load DAC0 with a 1000 ohm resistor from DAC0 to GND, and set DAC0 to 3.0V, the actual voltage at the DAC0 terminal will be about 3.0*1000/(50+1000) = 2.86V. For currents > 8mA, you increasingly get added droop due to the ability of the output buffer to drive substantial current close to the power rails.
[8] The output buffer will limit current to about 20mA and can maintain this value continuously without damage. Take, for example, a 100 ohm resistor from DAC0 to GND, with the internal source impedance of 50 ohms, and DAC0 set to 4.5V. A simple calculation would predict a current of 4.5/(50+150) = 30mA, but the output buffer will limit the current to 20mA. A simple calculation taking into account only the voltage droop due to the internal 50 ohm resistance would predict a voltage at the DAC0 terminal of 4.5*100/(50+100) = 3.0V, but since the current is limited to 20mA the actual voltage at DAC0 would be more like 100*0.02 = 2.0V.
T8
Table A4-3. T8 DAC Information. All specifications are at 25 °C and Vsupply = 5.0 V unless otherwise noted.
| Conditions | Min | Typical | Max | Units | |
|---|---|---|---|---|---|
| Nominal Output Range [1] | No Load | -0.1 | - | 10.3 | Volts |
| @ ±20 mA | -0.1 | - | 10.3 | Volts | |
| Resolution | - | - | 16 | - | Bits |
| Absolute Accuracy | 0V to 10V | - | ±0.01 | - | % FS |
| Load Regulation | 0.1 | 0.25 | mV / mA | ||
| Integral Linearity Error | - | - | ±2 | ±4 | counts |
| Differential Linearity Error | - | - | ±1 | ±2 | counts |
| Noise [2] | - | - | ±1 | - | counts |
| Source Impedance [3] | - | - | 50 | - | Ω |
| Current Limit | Sourced | 20 | mA | ||
| Slew Rate [4] | - | - | 2 | - | V/μs |
[1] DACs are intended to be 0-10V. Some headroom has been provided to ensure that the full range is usable.
[2] Specified with no load and set to 0 V. Noise will increase with load and voltage, to a maximum of 3 counts.
[3] The T8 will compensate for the voltage drops across its output impendance up to the current limit. Beyond the current limit, the output voltage be reduced to protect the circuitry.
[4] When the current limit is exceeded, the output voltage will be reduced to protect the DAC circuitry.