TimerCounter (UE9 Only)
Enables, configures, and reads the counters and timers.
Command: |
|
|
Byte |
|
|
0 | Checksum8 |
|
1 | 0xF8 |
|
2 | 0×0C |
|
3 | 0×18 |
|
4 | Checksum16 (LSB) |
|
5 | Checksum16 (MSB) |
|
6 | TimerClockDivisor (0 = ÷256) |
|
7 | EnableMask |
|
|
| Bit 7: UpdateConfig |
|
| Bit 4: Enable Counter1 |
|
| Bit 3: Enable Counter0 |
|
| Bits 2-0: Number of timers enabled |
8 | TimerClockBase |
|
|
| 0×00: 750 kHz |
|
| 0×01: System Clock |
|
| 0×02: Reserved |
|
| 0×03: Reserved |
|
| 0×03: Reserved |
9 | UpdateReset |
|
|
| Bit 7: Reset Counter1 |
|
| Bit 6: Reset Counter0 |
|
| Bit 5: UpdateReset Timer5 |
|
| Bit 4: UpdateReset Timer4 |
|
| Bit 3: UpdateReset Timer3 |
|
| Bit 2: UpdateReset Timer2 |
|
| Bit 1: UpdateReset Timer1 |
|
| Bit 0: UpdateReset Timer0 |
10 | Timer0Mode |
|
11-12 | Timer0Value |
|
13 | Timer1Mode |
|
14-15 | Timer1Value |
|
16 | Timer2Mode |
|
17-18 | Timer2Value |
|
19 | Timer3Mode |
|
20-21 | Timer3Value |
|
22 | Timer4Mode |
|
23-24 | Timer4Value |
|
25 | Timer5Mode |
|
26-27 | Timer5Value |
|
28 | Counter0Mode |
|
29 | Counter1Mode |
|
|
|
|
|
|
|
Response: |
|
|
Byte |
|
|
0 | Checksum8 |
|
1 | 0xF8 |
|
2 | 0×11 |
|
3 | 0×18 |
|
4 | Checksum16 (LSB) |
|
5 | Checksum16 (MSB) |
|
6 | Errorcode |
|
7 | EnableStatus |
|
8-11 | Timer0 |
|
12-15 | Timer1 |
|
16-19 | Timer2 |
|
20-23 | Timer3 |
|
24-27 | Timer4 |
|
28-31 | Timer5 |
|
32-35 | Counter0 |
|
36-39 | Counter1 |
|
EnableMask: If the UpdateConfig bit is 0, this parameter and the TimerClock parameters do nothing. If the UpdateConfig bit is 1, then the timers and counters are enabled and disabled as specified by the other bits. The lower 3 bits specify the number of timers enabled (0-6). Bits 3 and 4 are set to enable a counter, or cleared to disable a counter. Any enabled timers and counters will take over FIO lines in order, starting with FIO0. Counter1 is used internally by stream mode, but in such a case only uses an FIO line if master or slave stream mode is used. The counters are reset when enabled or disabled.
EnableStatus: Returns which timers and counters are enabled. Bit locations are the same as the UpdateReset byte.
TimerClockBase: The determines the timer base clock which is used by all output mode timers. The choices are a fixed 750 kHz clock source, or the system clock. The UE9 is by default in high power mode which means the system clock is fixed at 48 MHz. The UpdateConfig bit must be set to change this parameter.
TimerClockDivisor: The timer clock is divided by this value, or divided by 256 if this value is 0. The UpdateConfig bit must be set to change this parameter.
UpdateReset: Each bit of this parameter determines whether that timer or counter is set to a new value or reset. Reads are performed before reset.
Timer#Mode: These values are only updated if the UpdateConfig bit is set. Following are the values to pass to configure how a timer operates:
Timer Modes |
|
0 | 16-bit PWM output |
1 | 8-bit PWM output |
2 | Period input (32-bit, rising edges) |
3 | Period input (32-bit, falling edges) |
4 | Duty cycle input |
5 | Firmware counter input |
6 | Firmware counter input (with debounce) |
7 | Frequency output |
8 | Quadrature input |
9 | Timer stop input (odd timers only) |
10 | System timer low read |
11 | System timer high read |
12 | Period input (16-bit, rising edges) |
13 | Period input (16-bit, falling edges) |
Timer#Value: These values are only updated if the UpdateConfig or associated UpdateReset bit is 1. The meaning of this parameter varies with the timer mode. See Section 2.10 of the UE9 dafor further information.
Counter#Mode: Pass 0.
Timer#: Returns the values from the timer modules. This is the value before reset (if reset was done).
Counter#: Returns the current count from the counters if enabled. This is the value before reset (if reset was done).