2.10 - Timers/Counters [UE9 Datasheet]

The UE9 has 6 timers (Timer0-Timer5) and 2 counters (Counter0-Counter1). See our Configuration and Timers & Counters pseudocode pages for programming guidance.

When any of these timers or counters are enabled, they take over an FIO line in sequence (Timer0, Timer1, …, Timer5, Counter0, Counter1). If any one of the 8 timers/counters is enabled, it will take over FIO0. If any 2 are enabled, they will take over FIO0 and FIO1. If all 8 are enabled, they will take over all 8 FIO lines. Some examples:

1 Timer enabled, Counter0 disabled, Counter1 disabled
FIO0=Timer0

1 Timer enabled, Counter0 disabled, Counter1 enabled
FIO0=Timer0
FIO1=Counter1

6 Timers enabled, Counter0 enabled, Counter1 enabled
FIO0-FIO5=Timer0-Timer5
FIO6=Counter0
FIO7=Counter1

Timers and counters can appear on various pins, but other I/O lines never move. For example, Counter1 can appear anywhere from FIO0 to FIO7, depending on how many timers are enabled and whether Counter0 is enabled.

Applicable digital I/O are automatically configured as input or output as needed when timers and counters are enabled, and stay that way when the timers/counters are disabled.

Each counter (Counter0 or Counter1) consists of a 32-bit register that accumulates the number of falling edges detected on the external pin. If a counter is reset and read in the same function call, the read returns the value just before the reset.

Counter1 is used internally by stream mode, but in such a case only uses an FIO line if clock output or external triggering is used. If any timers/counters are being used while starting/stopping a stream, the possible interaction between timer/counter configuration and starting/stopping a stream needs to be considered.

The timers (Timer0-Timer5) have various modes available:

Table 2.10-1. UE9 Timer Modes

Index (Low-level & UD)
0	16-bit PWM output
1	8-bit PWM output
2	Period input (32-bit, rising edges)
3	Period input (32-bit, falling edges)
4	Duty cycle input
5	Firmware counter input
6	Firmware counter input (with debounce)
7	Frequency output
8	Quadrature input
9	Timer stop input (odd timers only)
10	System timer low read (Default mode)
11	System timer high read
12	Period input (16-bit, rising edges)
13	Period input (16-bit, falling edges)

Table 2.10-2. UE9 Timer Clock Options

TimerClockBase
0	750 kHz
1	48 MHz (System)

All timers use the same timer clock (which affects modes 0, 1, 2, 3, 4, 7, 12, and 13). The timer clock is determined by dividing the base clock by the clock divisor. The divisor has a range of 0-255, where 0 corresponds to a division of 256. There are 2 choices for the timer base clock.

The low level TimerCounter function has a bit called UpdateConfig that must be set to change the timer clock, timer modes, or number of timers/counters enabled. When this bit is set, all timers and counters are re-initialized. The LabJackUD driver automatically sets this bit if any write requests are executed related to mode, enabling/disabling, or clock configuration.

The low level TimerCounter function has UpdateReset bits for each timer that must be set to change the timer value. The LabJackUD driver automatically sets the appropriate bit when a value write is executed.

The low level TimerCounter function has Reset bits for each counter that must be set to reset the counter to zero. The LabJackUD automatically sets the appropriate bit when a reset request is executed.

Subsections

2.10.1 - Timer Mode Descriptions [UE9 Datasheet]

2.10.2 - Timer Operation/Performance Notes [UE9 Datasheet]