ReadDefaults (ReadCurrent)
The U3, U6, and UE9 each have a different ReadDefaults function. Reads the power-up defaults from flash (Read the current configuration).
U3
Command: |
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| Defaults Map |
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Byte |
| Block Number | Byte Offset | Description | Nominal Values |
0 | Checksum8 | 0 | 0-3 | Not Used | 0x00 |
1 | 0xF8 | 0 | 4 | FIO Directions | 0x00 |
2 | 0x01 | 0 | 5 | FIO States | 0xFF |
3 | 0x0E | 0 | 6 | FIO Analog | 0x00 |
4 | Checksum16 (LSB) | 0 | 7 | Not Used | 0x00 |
5 | Checksum16 (MSB) | 0 | 8 | EIO Directions | 0x00 |
6 | 0x00 | 0 | 9 | EIO States | 0xFF |
7 | bits[0:6] BlockNum 0-7 | 0 | 10 | EIO Analog | 0x00 |
| bit 7: 1 = ReadCurrent | 0 | 11 | Not Used | 0x00 |
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| 0 | 12 | CIO Directions | 0x00 |
Response: |
| 0 | 13 | CIO States | 0xFF |
Byte |
| 0 | 14-15 | Not Used | 0x00 |
0 | Checksum8 | 0 | 16 | Config Write Mask | 0x00 (NM) |
1 | 0xF8 | 0 | 17 | NumOfTimersEnabled | 0x00 |
2 | 0x01 | 0 | 18 | Counter Mask | 0x00 |
3 | 0x0E | 0 | 19 | Pin Offset | 0x04 |
4 | Checksum16 (LSB) | 0 | 20 | Options | 0x00 |
5 | Checksum16 (MSB) | 0 | 21-31 | Not Used | 0x00 |
6 | Errorcode | 1 | 0 (32) | Clock_Source | 0x02 |
7 | 0x00 | 1 | 1 (33) | Divisor | 0x00 |
8-39 | Data | 1 | 2-15 (33-47) | Not Used | 0x00 |
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| 1 | 16 (48) | TMR0 Mode | 0x0A |
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| 1 | 17 (49) | TMR0 Value L | 0x00 |
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| 1 | 18 (50) | TMR0 Value H | 0x00 |
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| 1 | 19 (51) | Not Used | 0x00 |
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| 1 | 20 (52) | TMR1 Mode | 0x0A |
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| 1 | 21 (53) | TMR1 Value L | 0x00 |
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| 1 | 22 (54) | TMR1 Value H | 0x00 |
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| 1 | 23-31 (55-63) | Not Used | 0x00 |
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| 2 | 0-15 (64-79) | Not Used | 0x00 |
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| 2 | 16-17 (80-81) | DAC0 (2 Bytes) | 0x0000 |
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| 2 | 18-19 (82-83) | Not Used | 0x00 |
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| 2 | 20-21 (84-85) | DAC1 (2 Bytes) | 0x0000 |
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| 2 | 22-31 (86-95) | Not Used | 0x00 |
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| 3 | 0-15 (96-111) | AIN Neg Channel | 0x1F |
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| 3 | 16-31 (112-127) | Not Used | 0x00 |
U6
Command: |
| Power-Up Defaults Address Map | |||
Byte |
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0 | Checksum8 | Block # | Byte # | Name | Factory |
1 | 0xF8 | 0 | 0-3 | Not Used | 0x00 |
2 | 0x01 | 0 | 4 | FIODirection | 0x00 |
3 | 0x0E | 0 | 5 | FIOState | 0xff |
4 | Checksum16 (LSB) | 0 | 6-7 | Not Used | 0x00 |
5 | Checksum16 (MSB) | 0 | 8 | EIODirection | 0x00 |
6 | 0x00 | 0 | 9 | EIOState | 0xff |
7 | bits[0:6] BlockNum 0-7 | 0 | 10-11 | Not Used | 0x00 |
| bit 7: 1=ReadCurrent | 0 | 12 | CIODirection | 0x00 |
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| 0 | 13 | CIOState | 0x0f |
Response: |
| 0 | 14-15 | Not Used | 0x00 |
Byte |
| 0 | 16 | Config Write Mask | 0x01 |
0 | Checksum8 | 0 | 17 | NumOfTimersEnabled | 0x00 |
1 | 0xF8 | 0 | 18 | Counter Mask | 0x00 |
2 | 0x11 | 0 | 19 | Pin Offset | 0x00 |
3 | 0x0E | 0 | 20-31 | Not Used | 0x00 |
4 | Checksum16 (LSB) | 1 | 0 (32) | Clock_Source | 0x02 |
5 | Checksum16 (MSB) | 1 | 1 (33) | Divisor | 0x00 |
6 | Errorcode | 1 | 2-15 (34-47) | Not Used | 0x00 |
7 | 0x00 | 1 | 16 (48) | TMR0 Mode | 0x0A |
8-39 | Data | 1 | 17 (49) | TMR0 Value L | 0x00 |
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| 1 | 18 (50) | TMR0 Value H | 0x00 |
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| 1 | 19 (51) | Not Used | 0x00 |
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| 1 | 20 (52) | TMR1 Mode | 0x0A |
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| 1 | 21 (53) | TMR1 Value L | 0x00 |
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| 1 | 22 (54) | TMR1 Value H | 0x00 |
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| 1 | 23 (55) | Not Used | 0x00 |
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| 1 | 24 (56) | TMR2 Mode | 0x0A |
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| 1 | 25 (57) | TMR2 Value L | 0x00 |
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| 1 | 26 (58) | TMR2 Value H | 0x00 |
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| 1 | 27 (59) | Not Used | 0x00 |
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| 1 | 28 (60) | TMR3 Mode | 0x0A |
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| 1 | 29 (61) | TMR3 Value L | 0x00 |
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| 1 | 30 (62) | TMR3 Value H | 0x00 |
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| 1 | 31 (63) | Not Used | 0x00 |
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| 2 | 0-15 (64-79) | Not Used | 0x00 |
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| 2 | 16-17 (80-81) | DAC0 (2 Bytes) | 0x00 |
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| 2 | 18-19 (82-83) | Not Used | 0x00 |
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| 2 | 20-21 (84-85) | DAC1 (2 Bytes) | 0x00 |
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| 2 | 22-31 (86-95) | Not Used | 0x00 |
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| 3 | 0-15 (96-111) | AIN Gain/Res | 0xF0 |
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| 3 | 16-31 (112-127) | AIN Options | 0x00 |
UE9
Command: |
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| Defaults Map |
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Byte |
| Block Number | Byte Offset | Description | Nominal Values |
0 | Checksum8 | 0 | 0-3 | Not Used | 0x00 |
1 | 0xF8 | 0 | 4 | FIO Directions | 0x00 |
2 | 0x01 | 0 | 5 | FIO States | 0xFF |
3 | 0x0E | 0 | 6 | EIO Directions | 0x00 |
4 | Checksum16 (LSB) | 0 | 7 | EIO States | 0xFF |
5 | Checksum16 (MSB) | 0 | 8 | CIO Directions | 0x00 |
6 | 0x00 | 0 | 9 | CIO States | 0xFF |
7 | bits[0:6] BlockNum 0-7 | 0 | 10 | MIO Directions | 0x00 |
| bit 7: 1 = ReadCurrent | 0 | 11 | MIO States | 0xFF |
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| 0 | 12-15 | Not Used | 0x00 |
Response: |
| 0 | 16 | Config Write Mask | 0x00 |
Byte |
| 0 | 17 | NumOfTimersEnabled | 0x00 |
0 | Checksum8 | 0 | 18 | Counter Mask | 0x00 |
1 | 0xF8 | 0 | 19 | Pin Offset | 0x00 |
2 | 0x11 | 0 | 20-31 | Not Used | 0x00 |
3 | 0x0E |
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4 | Checksum16 (LSB) | 1 | 0 (32) | Clock_Source | 0x02 |
5 | Checksum16 (MSB) | 1 | 1 (33) | Divisor | 0x00 |
6 | Errorcode | 1 | 2-15 (34-47) | Not Used | 0x00 |
7 | 0x00 | 1 | 16 (48) | TMR0 Mode | 0x0A |
8-39 | Data | 1 | 17 (49) | TMR0 Value L | 0x00 |
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| 1 | 18 (50) | TMR0 Value H | 0x00 |
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| 1 | 19 (51) | Not Used | 0x00 |
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| 1 | 20 (52) | TMR1 Mode | 0x0A |
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| 1 | 21 (53) | TMR1 Value L | 0x00 |
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| 1 | 22 (54) | TMR1 Value H | 0x00 |
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| 1 | 23 (55) | Not Used | 0x00 |
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| 1 | 24 (56) | TMR2 Mode | 0x0A |
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| 1 | 25 (57) | TMR2 Value L | 0x00 |
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| 1 | 26 (58) | TMR2 Value H | 0x00 |
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| 1 | 27 (59) | Not Used | 0x00 |
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| 1 | 28 (60) | TMR3 Mode | 0x0A |
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| 1 | 29 (61) | TMR3 Value L | 0x00 |
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| 1 | 30 (62) | TMR3 Value H | 0x00 |
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| 1 | 31 (63) | Not Used | 0x00 |
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| 2 | 0 (64) | TMR4 Mode | 0x0A |
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| 2 | 1 (65) | TMR4 Value L | 0x00 |
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| 2 | 2 (66) | TMR4 Value H | 0x00 |
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| 2 | 3 (65) | Not Used | 0x00 |
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| 2 | 4 (68) | TMR5 Mode | 0x0A |
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| 2 | 5 (69) | TMR5 Value L | 0x00 |
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| 2 | 6 (70) | TMR5 Value H | 0x00 |
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| 2 | 7-15 (71-79) | Not Used | 0x00 |
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| 2 | 16-17 (80-81) | DAC0 (2 Bytes) | 0x0000 |
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| 2 | 18-19 (82-83) | Not Used | 0x0000 |
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| 2 | 20-21 (84-85) | DAC1 (2 Bytes) | 0x0000 |
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| 2 | 22-31 (86-95) | Not Used | 0x00 |
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| 3 | 0-15 (96-111) | AIN Res | 0x12 |
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| 3 | 16-31 (112-127) | AIN BP/Gain | 0x00 |
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| 4 | 0-15 (128-143) | AIN Settling | 0x00 |
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| 4 | 16-31 (144-159) | Not Used | 0x00 |